In FinFETs, fins 101 are formed on a silicon substrate 103 with a shallow trench isolation (STI) region, or field oxide 105, between the fins, as illustrated in plan and cross-sectional views in FIGS. 1A and 1B, respectively. FIGS. 2A through 4A schematically illustrate plan views of process steps shown in FIGS. 2B through 4B and 2C through 4C, which illustrate cross-sectional views across the fins and along a dummy gate electrode, respectively. As illustrated in FIG. 2B, the fins 101 are revealed (e.g. to a depth of 30 nm to 60 nm), and in FIG. 2C, the dummy gate electrode 203 with hardmask 205 is formed. Adverting to FIG. 3B, the field oxide 105 may be partially etched away (as shown at 301) during post-gate cut processes such as cleaning steps with diluted hydrogen fluoride (dHF) and reactive ion etching (RIE) to form source/drain cavities, and even further, as shown in FIG. 4B at 401, with the use of SiCoNi material for cleaning the source/drain epitaxial growth interface and forming a recess for the epitaxial growth.
FIGS. 3C and 4C schematically illustrate formation of gate spacers 303 after the gate cut and clean. As illustrated in FIG. 5A, when the source/drain regions 501 are epitaxially grown, they may merge, as shown at 503, for standard fin pitch. Alternatively, for a large fin pitch, as illustrated in FIG. 5B, the oxide loss between the fins may dip down farther. Also, as illustrated in FIG. 5C, there may be a large loss of field oxide between two gate electrodes. The oxide loss may cause severe undercutting under the spacers, which in turn forms a pathway or channel from the dummy gate to the bottom silicon substrate through which, during removal of the dummy gate to form a replacement metal gate (RMG), gate-to-contact shorts may develop. Further, if the oxide loss is too large, the cavity for source/drain epitaxial growth will extend too deep, inducing short channel effects. Additionally, an uneven fin sidewall profile or remaining nitride spacer profile after source/drain RIE causes a non-uniform source/drain epitaxial profile.
A need therefore exists for methodology enabling a uniform epi profile with uniform fin sidewall spacers and with reduced field oxide loss and the resulting device.